The escalating demands for reducing thickness of oxide gate layers associated with ultra large scale integration require responsive changes in etching techniques. In MOS structures, polysilicon serves as the gate material. The gate length is a critical dimension that determines the channel lengths of devices. Thus, it is paramount that the etched linewidth dimension faithfully reproduces the dimension on the mask. A polysilicon etch process must, therefore, exhibit excellent linewidth control, and high uniformity of etching. In addition, a high degree of anisotropy is also generally required, as the doping of the source-drain and the polysilicon itself is typically performed by ion implantation.
If the etch process produces sloped sidewalls in the polysilicon, then portions of the gate would not be thick enough to effectively mask the substrate against the implantation. This would produce devices whose channel length depends on the degree of sidewall taper.
The degree of anisotropy is dictated by other considerations as well, including the extent of overetching required to remove stringers at the base of steep steps in the underlying topography, and the coverage of the etched polysilicon features by subsequently deposited layers. In the first of these cases, completely anisotropic etching will require extensive overetching to remove the stringers, while in the second, it will produce features that may be difficult for overlying films to cover.
Finally, the polysilicon layer is usually deposited over thin gate oxide, such as silicon dioxide, 50-500 .ANG. thick. Thus, the etch process should be selective over oxide etching, since if the oxide layer is removed, the shallow source-drain junction regions in the underlying silicon substrate would be rapidly etched by the reactants that cause polysilicon etching.
Typically, etching is conducted by utilizing an etching apparatus which generates a high-density plasma, e.g., a high-density chlorine plasma. Such a high-density plasma etching technique comprises feeding chlorine gas into an etching apparatus, such as a Transformer Coupled Plasma (TCP) source type of apparatus to generate a high-density plasma with Cl.sup.31 as the etching species. Other types of etching apparatus using other high-density plasma sources also can be used. For example, etching can be conducted with an Electron Cyclotron Resonance (ECR) type apparatus, a Helicon Resonant Inductive Coupled plasma source type apparatus or a Decoupled Plasma Source (DPS) type of apparatus.
A conventional etching technique is illustrated in FIGS. I through 3 with an example of manufacturing flash memory transistor devices. As illustrated in FIG. 1, an oxide layer 10, such as silicon dioxide, is formed on a semiconductor substrate (not shown). A polysilicon (poly-2) layer 12 is then formed on the oxide layer 10. The polysilicon layer 12 is used to form a gate of a flash memory transistor. The polysilicon layer 12 is covered with a layer 14 of conductive material, such as tungsten silicide. A cap polysilicon layer 16 is deposited on the conductive layer 14 to prevent the gate from lifting. An anti-reflecting coating 18, such as SiON, is formed on the cap polysilicon layer 16. A photo-resist mask 20 is next formed on the surface of the anti-reflecting coating 18. The photo-resist mask 20 comprises a pattern defining an area to be etched. The use of the layers 10-20 are conventional, as well as the technique for depositing the various layers.
Accordingly, the function and description of such known components and deposition techniques are not set forth herein in detail.
As depicted in FIG. 2, etching is then conducted to remove the layers covering the oxide layer in an area between flash memory transistors. Etching may be performed utilizing a high-density plasma, such as a high-density chlorine plasma generated by an etching apparatus into which chlorine gas is fed at a flow rate of about 50 sccm to about 200 sccm. The etching process is monitored in a conventional manner by optical spectrum monitoring.
Etching is continued until the poly-2 material is substantially removed. Then, as illustrated in FIG. 3, an etching process is performed to remove poly-2 residues. As a result, only oxide layer 10 remains on an open area between two flash memory transistors 22.
Such inherent factors of polysilicon etching, as the non-uniformity of the plasma, low sensitivity of the end point detection, and low selectivity of the etch process over oxide etching, adversely impact the control of oxide thickness uniformity. Therefore, the oxide layer 10 is partially removed during the poly etch process, and the remaining gate oxide layer will have non-uniform thickness. As the oxide layer 10 is very thin, its non-uniform thickness may result in damaging the underlying substrate during the etch process.
As gate oxide thickness has grown smaller with each generation of integrated circuits, it would be desirable to create an etching process that provides uniform gate oxide thickness and prevents the substrate from being damaged.